VHDL
Hardware description language / From Wikipedia, the free encyclopedia
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VHDL (VHSIC Hardware Description Language) is a hardware description language that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. The language was developed for the US military VHSIC program in the 1980s, and has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019. To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS (officially IEEE 1076.1) has been developed.
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Paradigm | concurrent, reactive, dataflow |
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First appeared | 1980s |
Stable release | IEEE 1076-2019
/ 23 December 2019; 4 years ago (2019-12-23) |
Typing discipline | strong |
Filename extensions | .vhd |
Website | IEEE VASG |
Dialects | |
VHDL-AMS | |
Influenced by | |
Ada,[1] Pascal | |
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